1. Field of the Invention
The present invention relates to laser thermal processing, and in particular relates to laser thermal processing in the formation of semiconductor devices.
2. Description of the Prior Art
Laser thermal processing (LTP) utilizes short pulses of laser radiation to thermally anneal and activate the dopants in semiconductors as part of the process of forming a semiconductor device, such as a metal oxide semiconductor (MOS) device. LTP is described in U.S. Pat. Nos. 5,908,307, 6,366,308 and 6,365,476, which patents are incorporated by reference herein. Dopant activation via LTP is achieved by melting a thin layer of semiconductor material to diffuse the dopants within the molten region. During cooling, the molten material re-crystallizes, fixing the dopants into the lattice sites where they remain electrically active.
The LTP technique can be used to form junctions in source and drain extension regions of a field-effect transistor (FET). The LTP-formed junctions have desirable characteristics, i.e., they are shallow, abrupt, and have low resistance. In addition, because of the extremely high heating and cooling rates involved in LTP (106-1012 Kelvin/sec), a meta-stable state can be established wherein dopant activation occurs above the solid-solubility limit. These properties allow a transistor to be scaled to a smaller dimension with improved performance.
In LTP, it is important to uniformly heat the structure being processed. To achieve uniform LTP heating of a MOS devices, a “switch layer” may be employed. A reflectivity-based switch layer is described in U.S. Pat. Nos. 6,303,476 and 6,383,956, which patents are incorporated by reference herein. A phase-based switch layer is described in U.S. Pat. No. 6,479,821, which patent is incorporated by reference herein.
FIG. 1 is a cross-sectional view of a prior art LTP structure 8 as formed on a silicon substrate 10 having a crystalline region 12 and an amorphous silicon layer (junction) 14 atop the crystalline region. LTP structure 8 includes a thin dielectric (e.g., silicon dioxide) layer 20 that resides atop amorphous silicon junction 14., LTP structure 8 also includes an absorber layer 24 (e.g., a metal layer such as titanium) that resides atop dielectric layer 20. Further, in the example embodiment shown, LTP structure 8 includes an optional switch layer 30 that resides atop the metal layer. Switch layer 30 has a transition temperature at which the layer changes its state.
Optional switch layer 30 is either a reflectivity-switch layer or a phase-switch layer. For a reflectivity-switch layer, the reflectivity of the switch layer increases dramatically when the switch occurs. Thus, LTP radiation that is transmitted by the switch while in the first state is reflected in the second state. An example material for a reflectivity-switch layer is polysilicon, which has a melting temperature about 200° C. higher than amorphous silicon.
For a phase-switch layer, the absorption of the layer changes dramatically when the switch occurs but the layer does not heat significantly due to a high latent heat of melting or vaporization. Thus, LTP radiation that is transmitted by the switch layer while in the first state is absorbed by the switch layer in the second state without increasing the temperature of the switch layer due to the latent heat of vaporization or melting. An example material for a phase-switch layer is aluminum arsenide, or layers of silicon dioxide and polyimide.
Dielectric layer 20 serves as a metal diffusion barrier, and also prevents metal from reacting with silicon junction 14. Absorber layer 24 serves to absorb laser radiation 40 and transfer heat to silicon junction 14, as well as to switch layer 30.
Switch layer 30 is used to regulate the junction temperature when structure 8 is irradiated with laser radiation 40. When structure 8 is first irradiated, the temperatures of switch layer 30 and junction 14 rise due to the heat emitted by absorber layer 24. When the temperature of junction 14 reaches its melting temperature (i.e., the melting temperature of amorphous silicon), the junction starts melting. When the temperature of switch layer 30 reaches its transition temperature, radiation 40 is substantially prevented from reaching absorber layer 24 by virtue of the change of the state of the switch layer (e.g., changing from low reflectivity to high reflectivity, or from low absorption to high absorption).
Therefore, the temperature of junction temperature 14 is prevented from exceeding the melting temperature of crystalline substrate 10, which needs to remain crystalline in order to maintain the integrity of structure 8.
The use of structure 8 makes LTP much easier to perform, i.e., it provides a greater process latitude. However, on certain types of device wafers, the upper limit of the process window is restricted by the possibility of melting select temperature-sensitive elements in the device. For example, in the case of a MOS transistor, the polysilicon gate (“poly-gate”) that resides atop the field oxide can melt, especially if a switch layer also made of polysilicon is employed. After melting and recrystallization using LTP processing, the poly-gate may deform and become incapable of performing its required function in the device.
Accordingly, there are two main requirements for performing LTP when forming certain types of IC devices, such as MOS transistors: (1) doped amorphous regions(s) need to be heated to their melting temperature, but not to a temperature higher than the crystal silicon melt temperature; and (2) any temperature-sensitive elements (e.g., poly-gates) cannot be heated to their melting temperature, and should be kept below their melting temperature.
Unfortunately, in the prior art process and structure described above in connection with FIG. 1, the amount of heat required to melt and activate the junction is often very close to the amount of heat needed to melt a temperature-sensitive element such as a poly-gate. The result is a relatively small LTP process window.
In forming a CMOS device, amorphization and dopant implant steps are performed to form the source and drain regions (extensions). But in the usual self-aligned source-drain formation process, the upper portion of the poly-gate will also be amorphized and/or doped during the implantation process to the same extent as the source and drains. Thus, the upper portion of the poly-gate also melts when the source and drain regions melt during LTP. This melting could deform the poly-gate, which typically ruins the device.
To fabricate devices such as MOSFETs and other types of integrated circuits (ICs) using LTP, it is highly desirable to keep the poly-gate temperature low and to prevent the amorphization of the polygate in order to preserve the poly-gate integrity.